1. Field of the Invention
The present invention relates to fabricating improved dielectric layers for semiconductor metallurgy systems, more specifically for fabricating a dielectric layer for separating and electrically isolating metallurgy layers on a integrated semiconductor device that has a planar surface and is void free.
2. Description of the Prior Art
More efficient utilization of device area in VLSI technology is a prominent objective. In order to decrease cost and increase the speed of operation, the size of the individual elements on integrated circuit semiconductor devices have been continuously reduced and packed closer together and the number of devices increased. The metallurgy system required to interconnect the elements had to undergo a similar reduction in size. Additional layers of metallurgy were also required to interconnect the larger number of elements on a single chip. As the number of metallurgy layers increased, and the passivation layers between the layers became thinner, the planarity of each successive layer was reduced. The exposure of resist layers used to fabricate the devices demanded a very fine and concise pattern. However, the depth of field of the exposure apparatus prevented the necessary precise pattern exposure because of the non planarity of the passivating layers. Techniques were developed to planarize the passivating layers, as is shown in FIGS. 1-4. An advanced technique consists of depositing a metallurgy pattern 10, using conventional photolithographic and etching techniques, on a insulating layer 11 supported on semiconductor substrate 12, as shown in FIG. 1. The metallurgy pattern 10 is then covered with a thin conformed layer 14, using chemical vapor deposition (CVD) techniques, as shown in FIG. 2. A non conformed layer 16 is deposited over layer 14 using spin-on-glass (SOG) techniques, which per se are well known. As shown in FIG. 3, layer 16 has a substantially planar top surface. However, when the spacing of the metallurgy lines of metallurgy pattern 10 is very small a void 18 can occur. The voids can occur at or below a 0.6 micrometer feature size. The voids occur because the spacing is so narrow that the spaces cannot be filled with the spin-on-glass material. The voids are objectionable because their presence in the final product causes poor reliability, that is failure during the use of the integrated circuit in the field. Conventionally, the SOG layer 16 is etched back to further planarize the surface and a layer 20 of silicon oxide, SiO.sub.2 is deposited, preferably by chemical vapor deposition (CVD) techniques, as shown in FIG. 4. With the etch back, and CVD layer 20, the void 18 has not been avoided.